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A25L80P
8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface
Preliminary
Document Title
8 Mbit, Low Voltage, Serial Flash Memory With 50MHz SPI Bus Interface Revision History
Rev. No.
0.0
History
Initial issue
Issue Date
May 30, 2005
Remark
PRELIMINARY
(May, 2005, Version 0.0)
AMIC Technology Corp.
A25L80P
8 Mbit, Low Voltage, Serial Flash Memory With 50 MHz SPI Bus Interface
GENERAL DESCRIPTION
The A25L80P is an 8 Mbit (1M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 16 sectors, each containing 256 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 4096 pages, or 1,048,576 bytes. The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.
Preliminary
FEATURES
8 Mbit of Flash Memory Flexible Sector Architecture (4/4/8/16/32)KB/64x15 KB Bulk Erase (8 Mbit) in 10s (typical) Sector Erase (512 Kbit) in 1s (typical) Page Program (up to 256 Bytes) in 3ms (typical) 2.7 to 3.6V Single Supply Voltage SPI Bus Compatible Serial Interface 50MHz Clock Rate (maximum) Deep Power-down Mode 1A (typical) Electronic Signature - JEDEC Standard (13h)
Pin Configurations SO8 Connections SO16 Connections
A25L80P A25L80P S Q W VSS 1 2 3 4 8 VCC 7 HOLD 6C 5D HOLD VCC DU DU DU DU S Q 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 C D DU DU DU DU VSS W
Note: DU = Do not Use
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Block Diagram
HOLD W S C D Q I/C Shift Register
Control Logic
High Voltage Generator
Address register and Counter
256 Byte Data Buffer
Status Register
FFFFFh
Y Decoder
Size of the read-only memory area
000FFh 00000h 256 Byte (Page Size) X Decoder
Pin Descriptions
Pin No. C D Q Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground Description
Logic Symbol
VCC
D C S W HOLD A25L80P
Q
S
W HOLD
Vcc Vss
VSS
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SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C). Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C). Chip Select ( S ). When this input signal is High, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select ( S ) Low enables the device, placing it in the active power mode. After Power-up, a falling edge on Chip Select ( S ) is required prior to the start of any instruction. Hold ( HOLD ). The Hold ( HOLD ) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select ( S ) driven Low. Write Protect ( W ). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register).
SPI MODES
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: - CPOL=0, CPHA=0 - CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 2, is the clock polarity when the bus master is in Stand-by mode and not transferring data: - C remains at 0 for (CPOL=0, CPHA=0) - C remains at 1 for (CPOL=1, CPHA=1)
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Figure 1. Bus Master and Memory Devices on the SPI Bus
SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) Bus Master (ST6, ST7, ST9, ST10, Other)
SDO SDI SCK CQD CQD CQD
SPI Memory Device CS3 CS2 CS1 S W HOLD
SPI Memory Device
SPI Memory Device
S
W HOLD
S
W HOLD
Note: The Write Protect ( W ) and Hold ( HOLD ) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL 0 1 CPHA 0 1 C C D Q MSB MSB
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OPERATING FEATURES Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP). To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch, BP2, BP1, and BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved, a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
Protection Modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the A25L80P boasts the following data protection mechanisms: Power-On Reset and an internal timer (tPUW) can provide protection against inadvertant changes while the power supply is outside the operating specification. Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Bulk Erase (BE) instruction completion The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM). The Write Protect ( W ) signal allows the Block Protect (BP2, BP1, BP0) bits and Status Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected Mode (HPM). In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertant Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction).
Active Power, Stand-by Power and Deep Power-Down Modes
When Chip Select ( S ) is Low, the device is enabled, and in the Active Power mode. When Chip Select ( S ) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to ICC1. The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to ICC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Electronic Signature (RES) instruction) is executed. All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.
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Table 1. Protected Area Sizes
Status Register Content BP2 Bit 0 0 0 0 1 1 1 1 BP1 Bit 0 0 1 1 0 0 1 1 BP0 Bit 0 1 0 1 0 1 0 1 none Upper sixteenth (sector 15) Upper eighth (two sectors: 14 and 15) Upper quarter (four sectors: 12 to 15) Upper half (eight sectors: 8 to 15) All sectors (eight sectors: 0 to 15) All sectors (eight sectors: 0 to 15) All sectors (eight sectors: 0 to 15) Protected Area
1
Memory Content Unprotected Area All sectors (sixteen sectors: 0 to 15) Lower fifteen-eighths (fifteen sectors: 0 to 14) Lower seven-eights (fourteen sectors: 0 to 13) Lower three-quarters (twelve sectors: 0 to 11) Lower half (eight sectors: 0 to 7) none none none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
Hold Condition
The Hold ( HOLD ) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress. To enter the Hold condition, the device must be selected, with Chip Select ( S ) Low. The Hold condition starts on the falling edge of the Hold ( HOLD ) signal, provided that this coincides with Serial Clock (C) being Low (as shown in Figure 3.). The Hold condition ends on the rising edge of the Hold ( HOLD ) signal, provided that this coincides with Serial Clock (C) being Low. If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes Low. This is shown in Figure 3. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. Normally, the device is kept selected, with Chip Select ( S ) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition. If Chip Select ( S ) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold ( HOLD ) High, and then to drive Chip Select ( S ) Low. This prevents the device from going back to the Hold condition.
Figure 3. Hold Condition Activation
C HOLD Hold Condition (standard use) Hold Condition (non-standard use)
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MEMORY ORGANIZATION
The memory is organized as: 1,048,576 bytes (8 bits each) 16 sectors (one (4/4/8/16/32) Kbytes & 64x15 Kbytes each) 4096 pages (256 bytes each). Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
Table 2. Memory Organization
Sector 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0-4 0-3 0-2 0-1 0-0 Sector Size (Kbytes) 64 64 64 64 64 64 64 64 64 64 64 64 64 64 64 32 16 8 4 4 F0000h E0000h D0000h C0000h B0000h A0000h 90000h 80000h 70000h 60000h 50000h 40000h 30000h 20000h 10000h 08000h 04000h 02000h 01000h 00000h Address Range FFFFFh EFFFFh DFFFFh CFFFFh BFFFFh AFFFFh 9FFFFh 8FFFFh 7FFFFh 6FFFFh 5FFFFh 4FFFFh 3FFFFh 2FFFFh 1FFFFh 0FFFFh 07FFFh 03FFFh 01FFFh 00FFFh
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INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select ( S ) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C). The instruction set is listed in Table 3. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, Read Device Identification and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select ( S ) can be driven High after any bit of the data-out sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select ( S ) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select ( S ) must driven High when the number of clock pulses after Chip Select ( S ) being driven Low is an exact multiple of eight. All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.
Table 3. Instruction Set
Instruction WREN WRDI RDSR WRSR READ FAST_READ PP SE BE DP RDID RES Description Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes Read Data Bytes at Higher Speed Page Program Sector Erase Bulk Erase Deep Power-down Read Device Identification Release from Deep Power-down, and Read Electronic Signature Release from Deep Power-down One-byte Instruction Code 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 1011 0000 0010 1101 1000 1100 0111 1011 1001 1001 1111 1010 1011 06h 04h 05h 01h 03h 0Bh 02h D8h C7h B9h 9Fh ABh Address Bytes 0 0 0 0 3 3 3 3 0 0 0 0 0 Dummy Bytes 0 0 0 0 0 1 0 0 0 0 0 3 0 Data Bytes 0 0 1 to 1 1 to 1 to 1 to 256 0 0 0 1 to 3 1 to 0
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Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4.) sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction. The Write Enable (WREN) instruction is entered by driving Chip Select ( S ) Low, sending the instruction code, and then driving Chip Select ( S ) High.
Figure 4. Write Enable (WREN) Instruction Sequence
S 0 C Instruction D High Impedance 1 23 45 6 7
Q
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5.) resets the Write Enable Latch (WEL) bit. The Write Disable (WRDI) instruction is entered by driving Chip Select ( S ) Low, sending the instruction code, and then driving Chip The Write Enable Latch (WEL) bit is reset under the following conditions:
Power-up

Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Page Program (PP) instruction completion Sector Erase (SE) instruction completion Bulk Erase (BE) instruction completion
Figure 5. Write Disable (WRDI) Instruction Sequence
S 0 C Instruction D High Impedance 1 23 45 6 7
Q
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Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 6. 0 no such cycle is in progress. WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 1.) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0. SRWD bit. The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect ( W ) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4. Status Register Format
b7 SRWD 0 0 BP2 BP1 BP0 WEL b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
The status and control bits of the Status Register are as follows: WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
Figure 6. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S 0 C Instruction D Status Register Out Q High Impedance 765 MSB 4 321 0 Status Register Out 76 MSB 5 4 3 21 0 7 1 234 56 78 9 10 11 12 13 14 15
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Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL). The Write Status Register (WRSR) instruction is entered by driving Chip Select ( S ) Low, followed by the instruction code and the data byte on Serial Data Input (D). The instruction sequence is shown in Figure 7. The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0. Chip Select ( S ) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select ( S ) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset. The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 1. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect ( W ) signal. The Status Register Write Disable (SRWD) bit and Write Protect ( W ) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered.
Figure 7. Write Status Register (WRSR) Instruction Sequence
S 0 C Instruction Status Register In 7 High Impedance 65 4 321 0 1 234 56 78 9 10 11 12 13 14 15
D Q
MSB
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Table 5. Protection Modes
W
Signal 1 0 1 SRWD Bit 0 0 1 Hardware Protected (HPM) Software Protected (SPM) Mode Write Protection of the Status Register Memory Content Protected Area1 Unprotected Area1
Status Register is Writable (if the WREN instruction has set the WEL bit) The values in the SRWD, BP2, BP1 and BP0 bits can be changed Status Register is Hardware write protected The values in the SRWD, BP2, BP1 and BP0 bits cannot be changed
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
0
1
Protected against Page Program, Sector Erase and Bulk Erase
Ready to accept Page Program and Sector Erase instructions
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
The protection features of the device are summarized in Table 5. When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect ( W ) is driven High or Low. When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of Write Protect ( W ): If Write Protect ( W ) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a
consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification. Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be entered: by setting the Status Register Write Disable (SRWD) bit after driving Write Protect ( W ) Low or by driving Write Protect ( W ) Low after setting the Status Register Write Disable (SRWD) bit. The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write Protect ( W ) High. If Write Protect ( W ) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.
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Read Data Bytes (READ)
The device is first selected by driving Chip Select ( S ) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fR, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 8. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes (READ) instruction is terminated by driving Chip Select ( S ) High. Chip Select ( S ) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 8. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S 0 C Instruction D High Impedance 24-Bit Address 23 22 21 MSB Q 76 MSB 3 2 1 0 Data Out 1 5 4 3 2 1 0 Data Out 2 7 1 234 56 78 9 10 28 29 30 31 32 33 34 35 36 37 38 39
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Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select ( S ) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency fC, during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 9. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select ( S ) High. Chip Select ( S ) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 9. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
S 0 C Instruction D High Impedance 24-Bit Address 23 22 21 MSB Q 3 2 1 0 1 234 56 78 9 10 28 29 30 31
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Dummy Byte D 76 5 4 3 21 0 Data Out 1 Q 76 MSB 5 4 3 2 1 0 76 MSB Data Out 2 5 4 3 2 1 0 7 MSB
Note: Address bits A23 to A20 are Don't Care.
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Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Page Program (PP) instruction is entered by driving Chip Select ( S ) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select ( S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 10. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. Chip Select ( S ) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed. As soon as Chip Select ( S ) is driven High, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see Table 2 and Table 1) is not executed.
Figure 10. Page Program (PP) Instruction Sequence
S 0 C Instruction D 24-Bit Address 23 22 21 MSB 3 2 1 0 76 MSB Data Byte 1 5 4 3 2 1 0 1 234 56 78 9 10 28 29 30 31 32 33 34 35 36 37 38 39
2072
2073
2074
2075
2076
2077 2
2078 1
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 C Data Byte 2 D 76 MSB 5 4 3 2 1 0 76 MSB Data Byte 3 5 4 3 2 1 0
Data Byte 256 76 MSB 5 4 3 0
Note: Address bits A23 to A20 are Don't Care.
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S
A25L80P
Sector Erase (SE)
The Sector Erase (SE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Sector Erase (SE) instruction is entered by driving Chip Select ( S ) Low, followed by the instruction code on Serial Data Input (D). Chip Select ( S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 11. Chip Select ( S ) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Sector Erase instruction is not executed. As soon as Chip Select ( S ) is driven High, the self-timed Sector Erase cycle (whose duration is tBE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Sector Erase (SE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Sector Erase (SE) instruction is ignored if one, or more, sectors are protected.
Figure 11. Sector Erase (SE) Instruction Sequence
S 0 C Instruction D 24-Bit Address 23 22 21 MSB 3 2 1 0 1 234 56 78 9 10 28 29 30 31
Notes: Address bits A23 to A20 are Don't Care.
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Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The Bulk Erase (BE) instruction is entered by driving Chip Select ( S ) Low, followed by the instruction code on Serial Data Input (D). Chip Select ( S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 12. Chip Select ( S ) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select ( S ) is driven High, the self-timed Bulk Erase cycle (whose duration is tBE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 12. Bulk Erase (BE) Instruction Sequence
S 0 C Instruction D 1 2 3 45 6 7
Notes: Address bits A23 to A20 are Don't Care.
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A25L80P
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write, Program and Erase instructions. Driving Chip Select ( S ) High deselects the device, and puts the device in the Standby mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, to reduce the standby current (from ICC1 to ICC2, as specified in DC Characteristics Table.). Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. This releases the device from this mode. The Release from Deep Power-down and Read Electronic Signature (RES) instruction also allows the Electronic Signature of the device to be output on Serial Data Output (Q). The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select ( S ) Low, followed by the instruction code on Serial Data Input (D). Chip Select ( S ) must be driven Low for the entire duration of the sequence. The instruction sequence is shown in Figure 13. Chip Select ( S ) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select ( S ) is driven High, it requires a delay of tDP before the supply current is reduced to ICC2 and the Deep Power-down mode is entered. Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 13. Deep Power-down (DP) Instruction Sequence
S 0 C Instruction D Stand-by Mode Deep Power-down Mode 1 2 3 45 6 7 tDP
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Read Device Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification code to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 37h, plus the continuation identification for AMIC Technology. The device identification is assigned by the device manufacturer, and indicates the memory in the first bytes (02h), and the memory capacity of the device in the second byte (13h). Any Read Identification (RDID) instruction while an Erase, or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select ( S ) Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 32-bit device identification, stored in the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 14. The Read Identification (RDID) instruction is terminated by driving Chip Select ( S ) High at any time during data output. When Chip Select ( S ) is driven High, the device is put in the Stand-by Power mode. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
Table. Read Identification (READ_ID) Data-Out Sequence Manufacture Identification Continuation ID 7Fh Manufacture ID 37h Device Identification Memory Type 02h Memory Capacity 13h
Figure 14. Read Identification (RDID) Data-Out Sequence
S
01 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 21 22 23 24 25 26 29 30 31 32 33 34 37 38 39
C
Instruction
D Q
High Impedance
31 30 29 26 25 24 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0
Continuation ID
Manufacture ID
Memory Type
Device ID
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Release from Deep Power-down and Read Electronic Signature (RES)
Once the device has entered the Deep Power-down mode, all instructions are ignored except the Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device out of the Deep Power-down mode. The instruction can also be used to read, on Serial Data Output (Q), the 8-bit Electronic Signature, whose value for the A25L80P is 13h. Except while an Erase, Program or Write Status Register cycle is in progress, the Release from Deep Power-down and Read Electronic Signature (RES) instruction always provides access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered. Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. The device is first selected by driving Chip Select ( S ) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial Data Input (D) during the rising edge of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C). The instruction sequence is shown in Figure 15. The Release from Deep Power-down and Read Electronic Signature (RES) instruction is terminated by driving Chip Select ( S ) High after the Electronic Signature has been read at least once. Sending additional clock cycles on Serial Clock (C), while Chip Select ( S ) is driven Low, cause the Electronic Signature to be output repeatedly. When Chip Select ( S ) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the Standby Power mode is delayed by tRES2, and Chip Select ( S ) must remain High for at least tRES2 (max), as specified in AC Characteristics Table . Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
Figure 15. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence and Data-Out Sequence
S 0 C Instruction D High Impedance 3 Dummy Butes 23 22 21 MSB Q 76 MSB Deep Power-down Mode Stand-by Mode 5 4 3 2 1 0 3 2 1 0 tRES2 1 234 56 78 9 10 28 29 30 31 32 33 34 35 36 37 38
Note: The value of the 8-bit Electronic Signature, for the A25L80P, is 13h.
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Figure 16. Release from Deep Power-down (RES) Instruction Sequence
S tRES1
C
0
1
2
3
45
6
7
D
Instruction
Q
High Impedance
Deep Power-down Mode
Stand-by Mode
Driving Chip Select ( S ) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in Figure 16.), still insures that the device is put into Stand-by Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in the Deep
Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES1, and Chip Select ( S ) must remain High for at least tRES1 (max), as specified in AC Characteristics Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
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A25L80P
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be selected (that is Chip Select ( S ) must follow the voltage applied on VCC) until VCC reaches the correct value: VCC (min) at Power-up, and then for a further delay of tVSL VSS at Power-down tPUW after VCC passed the VWI threshold - tVSL afterVCC passed the VCC(min) level These values are specified in Table 6. If the delay, tVSL, has elapsed, after VCC has risen above VCC(min), the device can be selected for READ instructions even if the tPUW delay is not yet fully elapsed. At Power-up, the device is in the following state: The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. Normal precautions must be taken for supply rail decoupling, to stabilize the VCC feed. Each device in a system should have the VCC rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of 0.1F). At Power-down, when VCC drops from the operating voltage, to below the POR threshold value, VWI, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a Power-down occurs while a Write, Program or Erase cycle is in progress, some data corruption can result.)
Usually a simple pull-up resistor on Chip Select ( S ) can be used to insure safe and proper Power-up and Power-down. To avoid data corruption and inadvertent write operations during power up, a Power On Reset (POR) circuit is included. The logic inside the device is held reset while VCC is less than the POR threshold value, VWI - all operations are disabled, and the device does not respond to any instruction. Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However, the correct operation of the device is not guaranteed if, by this time, VCC is still below VCC(min). No Write Status Register, Program or Erase instructions should be sent until the later of:
Figure 17-1. Power-up Timing
VCC
VCC(max)
VCC(min) tPU
Full Device Access
time
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Figure 17-2. Power-Down and Voltage Drop
VCC
VCC(max)
No Device Access Allowed
VCC(min) tPU
Device Access Allowed
VCC(low) tPD time
Table 6. Power-Up Timing and VWI Threshold
Symbol tVSL1 tPUW1 VWI1 VCC(min) to S low Time delay to Write instruction Write Inhibit Voltage Parameter Min. 10 1 1 10 2 Max. Unit s ms V
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0).
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Absolute Maximum Ratings*
Storage Temperature (TSTG) . . . . . . . . . . . . . -65C to + 150C Lead Temperature during Soldering (Note 1) Input and Output Voltage (with respect to Ground) (VID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to +4.0V Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . -0.6V to +4.0V Electrostatic Discharge Voltage (Human Body model) (VESD) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2000V to 2000V Notes: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly). 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500, R2=500 )
*Comments
Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the AMIC SURE Program and other relevant quality documents.
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Table 7. Operating Conditions
Symbol VCC TA Supply Voltage Ambient Operating Temperature Parameter Min. 2.7 -40 Max. 3.6 85 Unit V C
Table 8. Data Retention and Endurance
Parameter Erase/Program Cycles Data Retention At 85C At 85C Condition Min. Max. 100,000 20 Unit Cycles per sector Years
Note: 1. This is preliminary data
Table 9. Capacitance
Symbol COUT CIN Parameter Output Capacitance (Q) Input Capacitance (other pins) Test Condition VOUT = 0V VIN = 0V Min. Max. 8 6 Unit pF pF
Note: Sampled only, not 100% tested, at TA=25C and a frequency of 33 MHz.
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Table 10. DC Characteristics
Symbol ILI ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH Parameter Input Leakage Current Output Leakage Current Standby Current Deep Power-down Current Operating Current (READ) Operating Current (PP) Operating Current (WRSR) Operating Current (SE) Operating Current (BE) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6mA IOH = -100A VCC-0.2 Test Condition Min. Max. 2 2 Unit A A A A mA mA mA mA mA mA V V V V
S = VCC, VIN = VSS or VCC S = VCC, VIN = VSS or VCC
C= 0.1VCC / 0.9.VCC at 50MHz, Q = open C= 0.1VCC / 0.9.VCC at 33MHz, Q = open
50 10 8 4 15 15 15 15 -0.5 0.7VCC 0.3VCC VCC+0.4 0.4
S = VCC S = VCC S = VCC S = VCC
Note: 1. This is preliminary data at 85C Table 11. Instruction Times Symbol tW tPP tSE tBE Alt. Parameter Write Status Register Cycle Time Page Program Cycle Time Sector Erase Cycle Time Bulk Erase Cycle Time Min. Typ. 5 1.5 1 4.5 Max. 15 5 3 10 Unit ms ms s s
Note: 1. At 85C 2. This is preliminary data
Table 12. AC Measurement Conditions
Symbol CL Load Capacitance Input Rise and Fall Times Input Pulse Voltages Input Timing Reference Voltages Output Timing Reference Voltages Note: Output Hi-Z is defined as the point where data out is no longer driven. Parameter Min. 30 5 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC VCC / 2 Max. Unit pF ns V V V
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Figure 18. AC Measurement I/O Waveform
Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.5VCC 0.2VCC 0.3VCC
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Table 13. AC Characteristics
Symbol fC fR tCH tCL
1 1 5
Alt. fC
Parameter Clock Frequency for the following instructions: FAST_READ, PP, SE, BE, DP, RES, RDID, WREN, WRDI, RDSR, WRSR Clock Frequency for READ instructions Clock High Time Clock Low Time Clock Rise Time3 (peak to peak) Clock Fall Time3 (peak to peak)
Min.
Typ.
Max.5 50 33
Unit MHz MHz ns ns V/ns V/ns ns ns ns ns ns ns ns
D.C. D.C. 9 9 0.1 0.1 5 5 5 5 5 5 100
tCLH tCLL
tCLCH 2 tCHCL 2 tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL tSHQZ 2 tCLQV tCLQX tHLCH tCHHH tHHCH tCHHL tHHQX 2 tHLQZ 2 tWHSL 4 tSHWL 4 tDP
2
tCSS
S Active Setup Time (relative to C) S Not Active Hold Time (relative to C)
tDSU tDH
Data In Setup Time Data In Hold Time
S Active Hold Time (relative to C) S Not Active Setup Time (relative to C)
tCSH tDIS tV tHO
S Deselect Time
Output Disable Time Clock Low to Output Valid Output Hold Time
8 8 0 5 5 5 5 8 8 20 100 3 30 30 5 3 1 10 15 5 3 40
ns ns ns ns ns ns ns ns ns ns ns s s s ms ms s s
HOLD Setup Time (relative to C) HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C) HOLD Hold Time (relative to C) tLZ tHZ HOLD to Output Low-Z
HOLD to Output High-Z
Write Protect Setup Time Write Protect Hold Time
S High to Deep Power-down Mode S High to Standby Mode without Electronic Signature Read S High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time Page Program Cycle Time Sector Erase Cycle Time Bulk Erase Cycle Time
tRES1 2 tRES2 2 tW tpp tSE tBE
Note: 1. tCH + tCL must be greater than or equal to 1/ fC 2. Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
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Figure 19. Serial Input Timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN High Impedance tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
Figure 20. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W tSHSL S
tSHWL
C
D High Impedance
Q
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Figure 21. Hold Timing
S tHLCH
tCHHL
tHHCH
C
tCHHH
tHLQZ D Q HOLD
tHHQX
Figure 22. Output Timing
S tCH C tCLQV tCLQX D tQLQH tQHQL Q
ADDR.LSB IN
tCLQV tCLQX
tCL
LSB OUT
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Part Numbering Scheme
A25 X XX X X XX X X X
Package Material Blank: normal F: PB free
Temperature* Speed - MHz Operating Frequency Package MW = SOP8 MF = SOP16 Device Version*
Device Function P = Page Program & Sector Erase Device Density 05 = 512 Kbit 40 = 4 Mbit 80 = 8 Mbit 16 = 16 Mbit Device Voltage L = 2.7-3.6V
Device Type A25 = AMIC Serial Flash
* Optional
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Ordering Information
Part No. Speed (MHz) Active Read Current Typ. (mA) Program/Erase Current Typ. (mA) Standby Current Typ. (A) Package
A25L80PMW-50 A25L80PMW-50F 50 A25L80PMW-50U A25L80PMW-50UF A25L80PMF-50 A25L80PMF-50F 50 A25L80PMF-50U A25L80PMF-50UF 8 15 50 8 15 50
8 Pin SOP 8 Pin Pb-Free SOP 8 Pin SOP 8 Pin Pb-Free SOP 16 Pin SOP 16 Pin Pb-Free SOP 16 Pin SOP 16 Pin Pb-Free SOP
-U is for industrial operating temperature range: -40C ~ +85C
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Package Information
SOP 8L (209mil) Outline Dimensions unit: mm
8
5
1
4 C D
A2 A
0.25
e
A1
b
GAGE PLANE SEATING PLANE
L
Dimensions in mm Symbol A A1 A2 b C D E E1 e L 0.50 0 Min 1.75 0.05 1.70 0.35 0.19 5.13 7.70 5.18 Nom 1.95 0.15 1.80 0.42 0.20 5.23 7.90 5.28 1.27 BSC 0.65 0.80 8 Max 2.16 0.25 1.91 0.48 0.25 5.33 8.10 5.38
Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads
E1
E
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Package Information
SOP 16L (300mil) Outline Dimensions unit: inch
D 16 9
0.008 typ.
1 0.016 typ.
8 0.050 typ.
A
SEATING PLANE 0.004max. A1 L D
Dimensions in inch Symbol A A1 D E H L Min 0.093 0.004 0.398 0.291 0.394 0.016 0 Max 0.104 0.012 0.413 0.299 0.419 0.050 8
Notes: 1. Dimensions "D" does not include mold flash, protrusions or gate burrs. 2. Dimensions "E" does not include interlead flash, or protrusions.
0.02 x 45
H
E
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